An integrated circuit device may electrically alter the threshold voltage of its NMOS transistors by raising the Vss power rail voltage above the bulk (e.g., well, tub, or substrate) voltage of the integrated circuit substrate (sometimes referred to as a “virtual ground”). This technique is commonly used to reduce the power consumption of the integrated circuit device due to sub-threshold leakage. Generally, the integrated circuit device will have two or more independent voltage domains to service respective core logic circuits that have signal paths therebetween; some of these voltage domains may operate on the virtual ground, and other voltage domains may operate on true ground.
Separate voltage supplies may be used to connect to N-MOS and P-MOS bulk regions in multiple well CMOS technologies. Modification of these voltages with respect to the primary power and ground supplies is called well-biasing. These supplies can be modulated to provide a back-bias voltage which causes an increase in the MOS device threshold voltage, Vth, thereby reducing the sub-threshold leakage. Back-bias tap cells have a basic function to provide access to the wells and/or substrate independent of the source connected transistors therein. Back bias tap cells provide power for wells of always-on cells while power is gated for retention of flip-flops states, power gates with buffers and always-on buffers. They also provide well access such that back biasing can be used for leakage optimization.
One way to dramatically lower the current of an integrated circuit device in a sleep state is to raise the ground rail voltage used by standard cells above the substrate voltage, commonly referred to as back-biasing. This reduces leakage current. Another way to reduce current while in a sleep state is to utilize a low voltage regulator since a loosely regulated, lower voltage is sufficient to maintain the logic cell states. This reduces bias current of not only the voltage regulator but of supporting macro cells like a band gap voltage reference. The aforementioned two techniques cannot be combined since the low voltage regulator does not provide a high enough voltage to maintain adequate noise margin when standard cells are in a back-biased state. A normal voltage regulator must be used to maintain adequate noise margin.
One problem with implementing source back-biasing is that the effective voltage across the biased circuits decreases due to the ground (common source) voltage rising which in turn reduces the reliability of the biased circuits. For example, in a source-biased power domain in 180 nanometer technology, the ground rail, called virtual ground, is raised to approximately 0.6 volts, so it is necessary to supply 1.8 volts to the power rail to allow for 1.2 volts of noise margin. Presently, that requires that the main voltage regulator be in operation since the output voltage of a low voltage regulator in 180 nanometer technology, for example, is only 1.2 volts, leaving just 0.6 volts of noise margin which is insufficient.